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path: root/include/hw/riscv
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* hw/riscv: virt: Add optional ACLINT support to virt machineAnup Patel2021-09-211-0/+2
* sifive_u: Connect the SiFive PWM deviceAlistair Francis2021-09-211-1/+13
* hw/riscv: opentitan: Add the flash aliasAlistair Francis2021-07-151-0/+2
* hw/riscv: opentitan: Add the unimplement rv_core_ibex_periAlistair Francis2021-07-151-0/+1
* hw/riscv: OpenTitan: Connect the mtime and mtimecmp timerAlistair Francis2021-06-241-1/+4
* hw/riscv: Use macros for BIOS image namesBin Meng2021-06-081-0/+5
* hw/opentitan: Update the interrupt layoutAlistair Francis2021-05-111-8/+8
* hw/riscv: Connect Shakti UART to Shakti platformVijai Kumar K2021-05-111-0/+2
* riscv: Add initial support for Shakti C machineVijai Kumar K2021-05-111-0/+73
* hw/riscv: microchip_pfsoc: Map EMMC/SD mux registerBin Meng2021-03-221-0/+1
* hw/riscv: Add fw_cfg support to virtAsherah Connor2021-03-221-0/+2
* hw/riscv: migrate fdt field to generic MachineStateAlex Bennée2021-03-101-1/+0
* hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal valueBin Meng2021-03-041-1/+1
* hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng2021-03-041-0/+3
* hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng2021-03-041-0/+4
* riscv: Pass RISCVHartArrayState by pointerAlistair Francis2021-01-161-3/+3
* riscv/opentitan: Update the OpenTitan memory layoutAlistair Francis2020-12-171-6/+17
* hw/riscv: Use the CPU to determine if 32-bitAlistair Francis2020-12-171-3/+5
* hw/riscv: boot: Remove compile time XLEN checksAlistair Francis2020-12-171-3/+5
* riscv: virt: Remove target macro conditionalsAlistair Francis2020-12-171-6/+0
* riscv: spike: Remove target macro conditionalsAlistair Francis2020-12-171-6/+0
* hw/riscv: microchip_pfsoc: add QSPI NOR flashVitaly Wool2020-12-171-0/+3
* hw/riscv: microchip_pfsoc: Hook the I2C1 controllerBin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Correct DDR memory mapBin Meng2020-11-031-1/+4
* hw/riscv: microchip_pfsoc: Map the reserved memory at address 0Bin Meng2020-11-031-0/+1
* hw/riscv: microchip_pfsoc: Connect the SYSREG moduleBin Meng2020-11-031-0/+2
* hw/riscv: microchip_pfsoc: Connect the IOSCB moduleBin Meng2020-11-031-1/+3
* hw/riscv: microchip_pfsoc: Connect DDR memory controller modulesBin Meng2020-11-031-0/+5
* hw/riscv: Load the kernel after the firmwareAlistair Francis2020-10-221-0/+3
* hw/riscv: Add a riscv_is_32_bit() functionAlistair Francis2020-10-221-0/+2
* hw/riscv: Return the end address of the loaded firmwareAlistair Francis2020-10-221-4/+4
* hw/riscv: sifive_u: Allow specifying the CPUAlistair Francis2020-10-221-0/+1
* Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost2020-09-182-6/+2
* sifive_u: Rename memmap enum constantsEduardo Habkost2020-09-181-17/+17
* sifive_e: Rename memmap enum constantsEduardo Habkost2020-09-181-19/+19
* Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell2020-09-1313-642/+149
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| * hw/riscv: Move sifive_test model to hw/miscBin Meng2020-09-091-45/+0
| * hw/riscv: Move sifive_uart model to hw/charBin Meng2020-09-091-77/+0
| * hw/riscv: Move riscv_htif model to hw/charBin Meng2020-09-091-59/+0
| * hw/riscv: Move sifive_plic model to hw/intcBin Meng2020-09-091-81/+0
| * hw/riscv: Move sifive_clint model to hw/intcBin Meng2020-09-091-60/+0
| * hw/riscv: Move sifive_gpio model to hw/gpioBin Meng2020-09-093-78/+2
| * hw/riscv: Move sifive_u_otp model to hw/miscBin Meng2020-09-092-81/+1
| * hw/riscv: Move sifive_u_prci model to hw/miscBin Meng2020-09-092-92/+1
| * hw/riscv: Move sifive_e_prci model to hw/miscBin Meng2020-09-091-71/+0
| * hw/riscv: sifive_u: Connect a DMA controllerBin Meng2020-09-091-0/+11
| * hw/riscv: clint: Avoid using hard-coded timebase frequencyBin Meng2020-09-091-1/+3
| * hw/riscv: microchip_pfsoc: Hook GPIO controllersBin Meng2020-09-091-0/+3
| * hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMsBin Meng2020-09-091-0/+7
| * hw/riscv: microchip_pfsoc: Connect a DMA controllerBin Meng2020-09-091-0/+11
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