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* Disable AES-NI instructions in CPUID reportHEADmasterLouis Burda2023-02-081-0/+3
* i386/sev: Fix segfault retrieving SEV capabilitiesCarlos Bilbao2022-10-281-0/+1
* i386/sev: fill XCR0_IN/XSS_IN according to initial/base XSAVE stateMichael Roth2022-02-091-1/+4
* i386/sev: fix launch measurement crash for SEV-SNPMichael Roth2022-02-091-1/+3
* i386:sev: skip hashing the kernel for the SEV-SNP guestBrijesh Singh2021-10-271-0/+5
* i386/sev: update query-sev QAPI format to handle SEV-SNPMichael Roth2021-10-243-16/+38
* i386/sev: sev-snp: add support for CPUID validationMichael Roth2021-10-241-1/+154
* target/i386: add new EPYC CPU versions with updated cache_infoMichael Roth2021-10-241-0/+184
* target/i386: allow versioned CPUs to specify new cache_infoMichael Roth2021-10-241-3/+33
* target/i386: set SEV-SNP CPUID bit when SNP enabledMichael Roth2021-10-241-0/+1
* i386/sev: populate secrets and cpuid page and finalize the SNP launchBrijesh Singh2021-10-242-2/+109
* i386/sev: add support to encrypt BIOS when SEV-SNP is enabledBrijesh Singh2021-10-233-4/+55
* i386/sev: add the SNP launch start contextBrijesh Singh2021-10-232-1/+29
* i386/sev: initialize SNP contextBrijesh Singh2021-10-234-5/+34
* i386/sev: introduce 'sev-snp-guest' objectBrijesh Singh2021-10-231-1/+266
* linux-header: add the SNP specific commandBrijesh Singh2021-10-221-0/+6
* i386/sev: introduce "sev-common" type to encapsulate common SEV stateMichael Roth2021-10-131-137/+192
* target/s390x: move tcg_gen_insn_start to s390x_tr_insn_startRichard Henderson2021-10-121-2/+8
* target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2021-10-072-13/+21
* target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich2021-10-073-33/+0
* target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich2021-10-072-77/+21
* target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich2021-10-074-79/+15
* target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich2021-10-071-0/+6
* target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich2021-10-074-55/+18
* target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich2021-10-072-41/+50
* target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich2021-10-074-1/+65
* target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich2021-10-072-18/+24
* target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich2021-10-072-78/+0
* target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich2021-10-072-63/+0
* target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich2021-10-072-13/+23
* target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich2021-10-072-0/+8
* target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich2021-10-071-3/+5
* target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich2021-10-071-1/+1
* target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich2021-10-071-2/+4
* Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20211006' into stagingRichard Henderson2021-10-067-58/+78
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| * target/hexagon: Use tcg_constant_*Philippe Mathieu-Daudé2021-10-065-53/+25
| * target/hexagon: Remove unused TCG temporary from predicated loadsPhilippe Mathieu-Daudé2021-10-061-2/+0
| * Hexagon (target/hexagon) probe the stores in a packet at start of commitTaylor Simpson2021-10-063-3/+53
* | tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson2021-10-057-26/+26
* | tcg: Expand MO_SIZE to 3 bitsRichard Henderson2021-10-052-2/+2
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* target/xtensa: list cores in a text filePaolo Bonzini2021-10-053-2/+14
* hexagon: use env keyword argument to pass PYTHONPATHPaolo Bonzini2021-10-051-1/+2
* sev/i386: Introduce sev_add_kernel_loader_hashes for measured linux bootDov Murik2021-10-053-0/+154
* target/sh4: Use lookup_symbol in sh4_tr_disas_logRichard Henderson2021-10-041-1/+1
* i386: Change the default Hyper-V version to match WS2016Vitaly Kuznetsov2021-10-011-3/+3
* i386: Make Hyper-V version id configurableVitaly Kuznetsov2021-10-013-15/+33
* i386: Implement pseudo 'hv-avic' ('hv-apicv') enlightenmentVitaly Kuznetsov2021-10-014-1/+15
* i386: Move HV_APIC_ACCESS_RECOMMENDED bit setting to hyperv_fill_cpuids()Vitaly Kuznetsov2021-10-011-3/+6
* i386: Support KVM_CAP_HYPERV_ENFORCE_CPUIDVitaly Kuznetsov2021-10-013-0/+11
* i386: Support KVM_CAP_ENFORCE_PV_FEATURE_CPUIDVitaly Kuznetsov2021-10-013-0/+15
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