cachepc

Prime+Probe cache-based side-channel attack on AMD SEV-SNP protected virtual machines
git clone https://git.sinitax.com/sinitax/cachepc
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commit 22297cd9d96fa608ff6d166fa215ff503908e539
parent 5ad426b7b5859275739616e5f62041317b5511a1
Author: Louis Burda <quent.burda@gmail.com>
Date:   Thu,  9 Feb 2023 08:41:34 -0600

Most consistent version of prime self-tests

Diffstat:
Mcachepc/asm.S | 24++++++++++++++++++------
Mcachepc/cachepc.c | 6+++---
Mcachepc/macro.S | 4++++
3 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/cachepc/asm.S b/cachepc/asm.S @@ -28,6 +28,7 @@ SYM_FUNC_END(cpc_read_pmc) SYM_FUNC_START(cpc_stream_hwpf_test_asm) push %rbx + mfence wbinvd readpmc $0 %r8 @@ -55,10 +56,11 @@ SYM_FUNC_START(cpc_prime_test1_asm) mov cpc_ds, %r10 + mfence wbinvd readpmc $0 %r8 - prime_pass prime_test1_2 %r10 %r11 %r12 + prime_pass prime_test1 %r10 %r11 %r12 readpmc $0 %r9 mov %r9, %rax @@ -80,10 +82,10 @@ SYM_FUNC_START(cpc_prime_test2_asm) mov cpc_ds, %r10 + mfence wbinvd - # try to convince replacement policy to - # keep this line in + # try to convince replacement policy to keep this line in mov (%rdi), %rax mov (%rdi), %rax mov (%rdi), %rax @@ -92,10 +94,14 @@ SYM_FUNC_START(cpc_prime_test2_asm) mov (%rdi), %rax mov (%rdi), %rax + # need 4 passes to evict all lines (reset cache line scores) prime_pass prime_test2_1 %r10 %r11 %r12 + prime_pass prime_test2_2 %r10 %r11 %r12 + prime_pass prime_test2_3 %r10 %r11 %r12 + prime_pass prime_test2_4 %r10 %r11 %r12 readpmc $0 %r8 - prime_pass prime_test2_2 %r12 %r11 %r10 + prime_pass prime_test2 %r12 %r11 %r10 readpmc $0 %r9 mov %r9, %rax @@ -117,9 +123,10 @@ SYM_FUNC_START(cpc_prime_test3_asm) mov cpc_ds, %r10 + mfence wbinvd - barrier + # try to convince replacement policy to keep this line in mov (%rsi), %rax mov (%rsi), %rax mov (%rsi), %rax @@ -129,7 +136,11 @@ SYM_FUNC_START(cpc_prime_test3_asm) mov (%rsi), %rax mov (%rsi), %rax - prime_pass prime_test3 %r10 %r11 %r12 + # need 4 passes to evict all lines (reset cache line scores) + prime_pass prime_test3_1 %r10 %r11 %r12 + prime_pass prime_test3_2 %r10 %r11 %r12 + prime_pass prime_test3_3 %r10 %r11 %r12 + prime_pass prime_test3_4 %r10 %r11 %r12 readpmc $0 %r8 .rept L1_ASSOC @@ -152,6 +163,7 @@ SYM_FUNC_START(cpc_eviction_prio_test_asm) mov cpc_ds, %r10 + mfence wbinvd prime eviction_prio_test %r10 %r11 %r12 diff --git a/cachepc/cachepc.c b/cachepc/cachepc.c @@ -161,8 +161,8 @@ cpc_save_msrmts(struct cpc_cl *head) cl = head; do { if (cl->first) { - BUG_ON(cl->set >= L1_SETS); - BUG_ON(cl->line != 0); + WARN_ON(cl->set >= L1_SETS); + WARN_ON(cl->line != 0); if (cl->count > L1_ASSOC) { CPC_ERR("OOB count %llu for set %u\n", cl->count, cl->set); @@ -171,7 +171,7 @@ cpc_save_msrmts(struct cpc_cl *head) } cpc_msrmts[cl->set] = cl->count; } else { - BUG_ON(cl->count != 0); + WARN_ON(cl->count != 0); } cl->count = 0; diff --git a/cachepc/macro.S b/cachepc/macro.S @@ -42,9 +42,13 @@ # clobbers rax, rbx, rcx, rdx, cl_tmp, (cl_out) .macro prime name cl_in cl_tmp cl_out + mfence + wbinvd + prime_pass pass1_\name \cl_in \cl_tmp \cl_out prime_pass pass2_\name \cl_in \cl_tmp \cl_out prime_pass pass3_\name \cl_in \cl_tmp \cl_out + prime_pass pass4_\name \cl_in \cl_tmp \cl_out .endm # clobbers rax, rbx, rcx, rdx, cl_tmp1, cl_tmp2, pmc_tmp, pmc_tmp2