cachepc

Prime+Probe cache-based side-channel attack on AMD SEV-SNP protected virtual machines
git clone https://git.sinitax.com/sinitax/cachepc
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commit cb7c6b3d6767335d13892451c141cfb717807712
parent 5975ec7b44887ad54417218251e669cca14bde80
Author: Louis Burda <quent.burda@gmail.com>
Date:   Wed, 25 Jan 2023 20:21:40 +0100

Use mfence instead of lfence for memory barrier

Diffstat:
MMakefile | 2+-
Mcachepc/cachepc.c | 4+++-
Mcachepc/macro.S | 4++--
Mcachepc/uapi.h | 1+
4 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile @@ -57,7 +57,7 @@ load: prep: sudo sh -c "echo 0 > /proc/sys/kernel/watchdog" sudo cpupower frequency-set -d 3.7GHz -u 3.7GHz - sudo sh -c "echo 1 > /proc/irq/127/smp_affinity" + sudo bash -c "for f in /proc/irq/*/smp_affinity; do echo 1 > \$$f 2>/dev/null; done" util/%: util/%.c $(CACHEPC_UAPI) diff --git a/cachepc/cachepc.c b/cachepc/cachepc.c @@ -161,7 +161,9 @@ cachepc_save_msrmts(struct cacheline *head) do { if (cl->first) { BUG_ON(cl->cache_set >= L1_SETS); - WARN_ON(cl->count > L1_ASSOC); + if (cl->count > L1_ASSOC) + CPC_ERR("Read count %llu for set %u line %u", + cl->count, cl->cache_set, cl->cache_line); cachepc_msrmts[cl->cache_set] = cl->count; } else { BUG_ON(cl->count != 0); diff --git a/cachepc/macro.S b/cachepc/macro.S @@ -2,8 +2,8 @@ # clobbers rax, rbx, rcx, rdx .macro barrier - lfence # memory barrier - rdtsc # compiler barrier + mfence # memory barrier + rdtsc # serializing .endm # clobbers rax, rbx, rcx, rdx, (out) diff --git a/cachepc/uapi.h b/cachepc/uapi.h @@ -55,6 +55,7 @@ enum { CPC_TRACK_FAULT_NO_RUN, CPC_TRACK_EXEC, CPC_TRACK_FULL, + CPC_TRACK_AUTO_FULL, }; struct cpc_track_config {