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| author | Louis Burda <quent.burda@gmail.com> | 2022-07-04 16:26:35 +0200 |
|---|---|---|
| committer | Louis Burda <quent.burda@gmail.com> | 2022-07-04 16:26:35 +0200 |
| commit | cee2126b8f316677ebee57e19fe7d50d09c066d1 (patch) | |
| tree | 1fd0eb3e008ad9cdb138df93f450973ea69e05eb /src/device_conf.h | |
| download | cachepc-cee2126b8f316677ebee57e19fe7d50d09c066d1.tar.gz cachepc-cee2126b8f316677ebee57e19fe7d50d09c066d1.zip | |
Initial out-of-tree setup
Diffstat (limited to 'src/device_conf.h')
| -rwxr-xr-x | src/device_conf.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/device_conf.h b/src/device_conf.h new file mode 100755 index 0000000..e24d681 --- /dev/null +++ b/src/device_conf.h @@ -0,0 +1,29 @@ +#pragma once + +// TODO: Read from kernel headers + +// General settings +// #define PAGE_SIZE 4096 +#define PROCESSOR_FREQ 2900000000 + +// Cache related settings +#define CACHELINE_SIZE 64 +#define CACHE_GROUP_SIZE (PAGE_SIZE / CACHELINE_SIZE) + +// Addressing: +// - virtual: 0 +// - physical: 1 +#define L1_ADDRESSING 0 +#define L1_SETS 64 +#define L1_ASSOCIATIVITY 8 +#define L1_ACCESS_TIME 4 + +#define L2_ADDRESSING 1 +#define L2_SETS 512 +#define L2_ASSOCIATIVITY 8 +#define L2_ACCESS_TIME 12 + +#define L3_ADDRESSING 1 +#define L3_SETS 4096 +#define L3_ASSOCIATIVITY 16 +#define L3_ACCESS_TIME 30 |
