Vincent' working single eviction test

5 files changed, 19 insertions, 12 deletions

diff --git a/src/asm.h b/src/asm.h
index 3498f2c..101faa9 100755
--- a/src/asm.h
+++ b/src/asm.h
@@ -36,7 +36,7 @@ cachepc_readpmc(uint64_t event)
 		: "c"(event)
 	);
 
-	return ((uint64_t) hi << 32) | lo;
+	return ((uint64_t) hi << 32) | (uint64_t)lo;
 }
 
 void
@@ -58,7 +58,7 @@ cachepc_lfence(void)
 	);
 }
 
-void
+inline void
 cachepc_sfence(void)
 {
 	asm volatile(
@@ -67,7 +67,7 @@ cachepc_sfence(void)
 	);
 }
 
-void
+inline void
 cachepc_mfence(void)
 {
 	asm volatile(
@@ -76,7 +76,7 @@ cachepc_mfence(void)
 	);
 }
 
-void
+inline void
 cachepc_readq(void *p)
 {
 	asm volatile (
@@ -85,7 +85,7 @@ cachepc_readq(void *p)
 	);
 }
 
-void
+inline void
 cachepc_victim(void *p)
 {
 	cachepc_mfence();
diff --git a/src/cachepc.c b/src/cachepc.c
index 62452a8..c7e6048 100755
--- a/src/cachepc.c
+++ b/src/cachepc.c
@@ -24,10 +24,10 @@ cachepc_init_counters(void)
 	 *
 	 * 6 slots total
 	 */
-       
+
 	reg_addr = 0xc0010200;
-	event_no = 0x64;
-	event_mask = 0x08;
+	event_no = 0x64;//0x29;//0x64;
+	event_mask = 0x08; //0x07; //0x08;
 	event = event_no | (event_mask << 8);
 	event |= (1ULL << 17); /* OS (kernel) events only */
 	event |= (1ULL << 22); /* enable performance counter */
diff --git a/src/cachepc.h b/src/cachepc.h
index 8c73249..ccdd2c0 100755
--- a/src/cachepc.h
+++ b/src/cachepc.h
@@ -103,6 +103,7 @@ cachepc_probe(cacheline *start_cl)
 {
 	uint64_t pre1, pre2;
 	uint64_t post1, post2;
+	volatile int i = 0;
 	cacheline *next_cl;
 	cacheline *curr_cl;
 
@@ -112,6 +113,11 @@ cachepc_probe(cacheline *start_cl)
 		cachepc_cpuid();
 		cachepc_mfence();
 	
+		pre1 = cachepc_readpmc(L2_HIT_CNTR);
+		pre2 = cachepc_readpmc(L2_MISS_CNTR);
+		
+		cachepc_cpuid();
+		cachepc_mfence();
 		asm volatile(
 			"mov 8(%[curr_cl]), %%rax \n\t"              // +8
 			"mov 8(%%rax), %%rcx \n\t"                   // +16
@@ -130,13 +136,13 @@ cachepc_probe(cacheline *start_cl)
 		cachepc_cpuid();
 		cachepc_mfence();
 
-		pre1 = cachepc_readpmc(L2_HIT_CNTR);
-		pre2 = cachepc_readpmc(L2_MISS_CNTR);
 
 		cachepc_cpuid();
 		cachepc_mfence();
-
-		msleep(100);
+		
+		//msleep(100);
+		//for(i=0; i<100000; ++i){
+		//}
 
 		post1 = cachepc_readpmc(L2_HIT_CNTR);
 		cachepc_cpuid();
@@ -147,6 +153,7 @@ cachepc_probe(cacheline *start_cl)
 		curr_cl->count = 0;
 		curr_cl->count += post1 - pre1;
 		curr_cl->count += post2 - pre2;
+		curr_cl = next_cl;
 	} while (__builtin_expect(curr_cl != start_cl, 1));
 
 	return curr_cl->next;
diff --git a/src/util.c b/src/util.c
index 5ad3efa..5ad3efa 100644..100755
--- a/src/util.c
+++ b/src/util.c
diff --git a/src/util.h b/src/util.h
index 7b543aa..7b543aa 100644..100755
--- a/src/util.h
+++ b/src/util.h