diff options
Diffstat (limited to 'kmod')
| -rwxr-xr-x | kmod/asm.h | 19 | ||||
| -rwxr-xr-x | kmod/cachepc.c | 43 | ||||
| -rwxr-xr-x | kmod/cachepc.h | 33 | ||||
| -rw-r--r-- | kmod/cachepc_user.h | 5 |
4 files changed, 38 insertions, 62 deletions
@@ -5,9 +5,6 @@ #define CPUID_AFFECTED_REGS "rax", "rbx", "rcx", "rdx" __attribute__((always_inline)) -static inline uint64_t cachepc_readpmc(uint64_t event); - -__attribute__((always_inline)) static inline void cachepc_cpuid(void); __attribute__((always_inline)) @@ -22,22 +19,6 @@ static inline void cachepc_mfence(void); __attribute__((always_inline)) static inline void cachepc_readq(void *p); -uint64_t -cachepc_readpmc(uint64_t event) -{ - uint32_t lo, hi; - - event = 0xC0010201 + 2 * event; - - asm volatile ( - "rdmsr" - : "=a" (lo), "=d" (hi) - : "c"(event) - ); - - return ((uint64_t) hi << 32) | (uint64_t) lo; -} - void cachepc_cpuid(void) { diff --git a/kmod/cachepc.c b/kmod/cachepc.c index 702cfad..ed36ac7 100755 --- a/kmod/cachepc.c +++ b/kmod/cachepc.c @@ -18,49 +18,28 @@ static uint16_t get_virt_cache_set(cache_ctx *ctx, void *ptr); static void *aligned_alloc(size_t alignment, size_t size); void -cachepc_init_counters(void) +cachepc_init_pmc(uint8_t index, uint8_t event_no, uint8_t event_mask) { - uint64_t event, event_no, event_mask; + uint64_t event; uint64_t reg_addr; - /* SEE: https://developer.amd.com/resources/developer-guides-manuals (PPR 17H 31H, P.166) + /* REF: https://developer.amd.com/resources/developer-guides-manuals (PPR 17H 31H, P.166) * - * performance event selection is done via 0xC001_020X with X = (0..A)[::2] - * performance event reading is done viea 0XC001_020X with X = (1..B)[::2] - * - * 6 slots total + * performance event selection via 0xC001_020X with X = (0..A)[::2] + * performance event reading viea 0XC001_020X with X = (1..B)[::2] */ - reg_addr = 0xc0010200; - event_no = 0x70; - event_mask = 0xFF; - event = event_no | (event_mask << 8); - event |= (1ULL << 17); /* OS (kernel) events only */ - event |= (1ULL << 22); /* enable performance counter */ - event |= (1ULL << 40); /* Host events only */ - printk(KERN_WARNING "CachePC: Initialized event %llu\n", event); - asm volatile ("wrmsr" : : "c"(reg_addr), "a"(event), "d"(0x00)); + WARN_ON(index >= 6); + if (index >= 6) return; - reg_addr = 0xc0010202; - event_no = 0x71; - event_mask = 0xFF; - event = event_no | (event_mask << 8); - event |= (1ULL << 17); /* OS (kernel) events only */ - event |= (1ULL << 22); /* enable performance counter */ - event |= (1ULL << 40); /* Host events only */ - printk(KERN_WARNING "CachePC: Initialized event %llu\n", event); - asm volatile ("wrmsr" : : "c"(reg_addr), "a"(event), "d"(0x00)); - - reg_addr = 0xc0010204; - event_no = 0x72; - event_mask = 0xFF; - event = event_no | (event_mask << 8); + reg_addr = 0xc0010200 + index * 2; + event = event_no | (event_mask << 8); event |= (1ULL << 17); /* OS (kernel) events only */ event |= (1ULL << 22); /* enable performance counter */ event |= (1ULL << 40); /* Host events only */ - printk(KERN_WARNING "CachePC: Initialized event %llu\n", event); + printk(KERN_WARNING "CachePC: Initialized %i. PMC %02X:%02X\n", + index, event_no, event_mask); asm volatile ("wrmsr" : : "c"(reg_addr), "a"(event), "d"(0x00)); - } cache_ctx * diff --git a/kmod/cachepc.h b/kmod/cachepc.h index a88edb8..5deb712 100755 --- a/kmod/cachepc.h +++ b/kmod/cachepc.h @@ -5,7 +5,7 @@ #include "util.h" #include "cachepc_user.h" -void cachepc_init_counters(void); +void cachepc_init_pmc(uint8_t index, uint8_t event_no, uint8_t event_mask); cache_ctx *cachepc_get_ctx(cache_level cl); void cachepc_release_ctx(cache_ctx *ctx); @@ -31,6 +31,9 @@ static inline cacheline *cachepc_probe(cacheline *head); __attribute__((always_inline)) static inline void cachepc_victim(void *p); +__attribute__((always_inline)) +static inline uint64_t cachepc_read_pmc(uint64_t event); + extern uint16_t *cachepc_msrmts; extern size_t cachepc_msrmts_count; @@ -46,8 +49,6 @@ cachepc_prime(cacheline *head) { cacheline *curr_cl; - //printk(KERN_WARNING "CachePC: Priming..\n"); - cachepc_cpuid(); curr_cl = head; do { @@ -56,8 +57,6 @@ cachepc_prime(cacheline *head) } while(curr_cl != head); cachepc_cpuid(); - //printk(KERN_WARNING "CachePC: Priming done\n"); - return curr_cl->prev; } @@ -102,8 +101,8 @@ cachepc_probe(cacheline *start_cl) curr_cl = start_cl; do { - pre = cachepc_readpmc(0); - pre += cachepc_readpmc(1); + pre = cachepc_read_pmc(0); + pre += cachepc_read_pmc(1); cachepc_mfence(); cachepc_cpuid(); @@ -126,8 +125,8 @@ cachepc_probe(cacheline *start_cl) cachepc_mfence(); cachepc_cpuid(); - post = cachepc_readpmc(0); - post += cachepc_readpmc(1); + post = cachepc_read_pmc(0); + post += cachepc_read_pmc(1); cachepc_mfence(); cachepc_cpuid(); @@ -148,3 +147,19 @@ cachepc_victim(void *p) cachepc_mfence(); cachepc_readq(p); } + +uint64_t +cachepc_read_pmc(uint64_t event) +{ + uint32_t lo, hi; + + event = 0xC0010201 + 2 * event; + + asm volatile ( + "rdmsr" + : "=a" (lo), "=d" (hi) + : "c"(event) + ); + + return ((uint64_t) hi << 32) | (uint64_t) lo; +} diff --git a/kmod/cachepc_user.h b/kmod/cachepc_user.h index cb4e921..a04b184 100644 --- a/kmod/cachepc_user.h +++ b/kmod/cachepc_user.h @@ -3,5 +3,6 @@ #include <linux/ioctl.h> #define CACHEPC_IOCTL_MAGIC 0xBF -#define CACHEPC_IOCTL_ACCESS_TEST _IOR(CACHEPC_IOCTL_MAGIC, 0, int) -#define CACHEPC_IOCTL_EVICTION_TEST _IOR(CACHEPC_IOCTL_MAGIC, 1, int) +#define CACHEPC_IOCTL_TEST_ACCESS _IOR(CACHEPC_IOCTL_MAGIC, 0, uint32_t) +#define CACHEPC_IOCTL_TEST_EVICTION _IOWR(CACHEPC_IOCTL_MAGIC, 1, uint32_t) +#define CACHEPC_IOCTL_INIT_PMC _IOW(CACHEPC_IOCTL_MAGIC, 2, uint32_t) |