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-rwxr-xr-xsrc/asm.h72
1 files changed, 72 insertions, 0 deletions
diff --git a/src/asm.h b/src/asm.h
new file mode 100755
index 0000000..9509952
--- /dev/null
+++ b/src/asm.h
@@ -0,0 +1,72 @@
+#pragma once
+
+#include <linux/kernel.h>
+
+#define CPUID_AFFECTED_REGS "rax", "rbx", "rcx", "rdx"
+
+__attribute__((always_inline))
+static inline uint64_t cachepc_readpmc(uint64_t event);
+
+__attribute__((always_inline))
+static inline void cachepc_cpuid(void);
+
+__attribute__((always_inline))
+static inline void cachepc_lfence(void);
+
+__attribute__((always_inline))
+static inline void cachepc_sfence(void);
+
+__attribute__((always_inline))
+static inline void cachepc_mfence(void);
+
+uint64_t
+cachepc_readpmc(uint64_t event)
+{
+ uint32_t lo, hi;
+
+ asm volatile (
+ "mov %[event], %%rcx\t\n"
+ "rdpmc\t\n"
+ : "=a" (lo), "=d" (hi)
+ : [event] "r" (event)
+ );
+
+ return ((uint64_t) hi << 32) | lo;
+}
+
+void
+cachepc_cpuid(void)
+{
+ asm volatile(
+ "mov $0x80000005, %%eax\n\t"
+ "cpuid\n\t"
+ ::: CPUID_AFFECTED_REGS
+ );
+}
+
+void
+cachepc_lfence(void)
+{
+ asm volatile(
+ "lfence\n\t"
+ ::
+ );
+}
+
+void
+cachepc_sfence(void)
+{
+ asm volatile(
+ "sfence\n\t"
+ ::
+ );
+}
+
+void
+cachepc_mfence(void)
+{
+ asm volatile(
+ "mfence\n\t"
+ ::
+ );
+}