blob: 95099527cc53ba728ef78b9bc6f5301e6c5b8f2f (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
|
#pragma once
#include <linux/kernel.h>
#define CPUID_AFFECTED_REGS "rax", "rbx", "rcx", "rdx"
__attribute__((always_inline))
static inline uint64_t cachepc_readpmc(uint64_t event);
__attribute__((always_inline))
static inline void cachepc_cpuid(void);
__attribute__((always_inline))
static inline void cachepc_lfence(void);
__attribute__((always_inline))
static inline void cachepc_sfence(void);
__attribute__((always_inline))
static inline void cachepc_mfence(void);
uint64_t
cachepc_readpmc(uint64_t event)
{
uint32_t lo, hi;
asm volatile (
"mov %[event], %%rcx\t\n"
"rdpmc\t\n"
: "=a" (lo), "=d" (hi)
: [event] "r" (event)
);
return ((uint64_t) hi << 32) | lo;
}
void
cachepc_cpuid(void)
{
asm volatile(
"mov $0x80000005, %%eax\n\t"
"cpuid\n\t"
::: CPUID_AFFECTED_REGS
);
}
void
cachepc_lfence(void)
{
asm volatile(
"lfence\n\t"
::
);
}
void
cachepc_sfence(void)
{
asm volatile(
"sfence\n\t"
::
);
}
void
cachepc_mfence(void)
{
asm volatile(
"mfence\n\t"
::
);
}
|