summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
...
| | | | | * | clk: qcom: gcc: Add GPU and NPU clocks for SM8150Vinod Koul2020-05-141-0/+64
| | | | | * | clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdscBjorn Andersson2020-05-141-0/+2
| | | | | * | clk: qcom: gdsc: Handle GDSC regulator suppliesBjorn Andersson2020-05-142-0/+27
| | | | | * | clk: qcom: msm8916: Fix the address location of pll->config_regBryan O'Donoghue2020-04-211-4/+4
| | | | | |/
| | | | * | clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unusedStephen Boyd2020-05-281-1/+1
| | | | * | clk: X1000: Add FIXDIV for SSI clock of X1000.周琰杰 (Zhou Yanjie)2020-05-281-6/+111
| | | | * | clk: Ingenic: Add CGU driver for X1830.周琰杰 (Zhou Yanjie)2020-05-283-0/+459
| | | | * | clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)2020-05-287-4/+41
| | | | * | clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)2020-05-281-11/+1
| | | | |/
| | | * | clk: intel: remove redundant initialization of variable rate64Colin Ian King2020-05-281-1/+1
| | | * | clk: intel: Add CGU clock driver for a new SoCRahul Tanwar2020-05-267-0/+1612
| | | |/
| | * | clk: mmp2: Add audio clock controller driverLubomir Rintel2020-05-273-0/+450
| | * | clk: mmp2: Add support for power islandsLubomir Rintel2020-05-274-1/+168
| | * | clk: mmp2: Add the audio clockLubomir Rintel2020-05-271-0/+4
| | * | clk: mmp2: Add the I2S clocksLubomir Rintel2020-05-271-0/+46
| | * | clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init()Lubomir Rintel2020-05-271-2/+2
| | * | clk: mmp2: Move thermal register defines up a bitLubomir Rintel2020-05-271-4/+4
| | * | clk: mmp: frac: Allow setting bits other than the numerator/denominatorLubomir Rintel2020-05-272-0/+4
| | * | clk: mmp: frac: Do not lose last 4 digits of precisionLubomir Rintel2020-05-271-8/+16
| | |/
| | |
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| *-------. \ Merge branches 'clk-unisoc', 'clk-trivial', 'clk-bcm', 'clk-st' and 'clk-ast2...Stephen Boyd2020-06-0110-66/+136
| |\ \ \ \ \ \
| | | | | | * | clk: ast2600: Fix AHB clock divider for A1Eddie James2020-05-271-6/+25
| | | | | | |/
| | | | | * / clk: clk-flexgen: fix clock-critical handlingAlain Volmat2020-05-271-0/+1
| | | | | |/
| | | | * | clk: bcm2835: Constify struct debugfs_reg32Rikard Falkeborn2020-05-271-3/+3
| | | | * | clk: bcm2835: Remove casting to bcm2835_clk_registerNathan Chancellor2020-05-261-31/+37
| | | | * | clk: bcm2835: Fix return type of bcm2835_register_gateNathan Chancellor2020-05-261-5/+5
| | | | |/
| | | * | clk: versatile: remove redundant assignment to pointer clkColin Ian King2020-05-261-1/+1
| | | * | clk: clk-xgene: Fix a typo in KconfigChristophe JAILLET2020-05-051-1/+1
| | | * | clk: Remove unused inline function clk_debug_reparentYueHaibing2020-05-051-4/+0
| | | |/
| | * | clk: sprd: add mipi_csi_xx gate clocksChunyan Zhang2020-05-261-0/+32
| | * | clk: sprd: check its parent status before reading gate clockChunyan Zhang2020-05-262-0/+16
| | * | clk: sprd: return correct type of value for _sprd_pll_recalc_rateChunyan Zhang2020-05-261-1/+1
| | * | clk: sprd: mark the local clock symbols staticChunyan Zhang2020-05-261-16/+16
| | |/
| | |
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| *---------. \ Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91' ...Stephen Boyd2020-06-0152-346/+1805
| |\ \ \ \ \ \ \
| | | | | | | * | clk: ti: dra7: remove two unused symbolsJason Yan2020-05-261-9/+0
| | | | | | | * | clk: ti: dra7xx: fix RNG clock parentTero Kristo2020-05-141-1/+1
| | | | | | | * | clk: ti: dra7xx: mark MCAN clock as DRA76x onlyTero Kristo2020-05-141-1/+1
| | | | | | | * | clk: ti: dra7xx: fix gpu clkctrl parentTero Kristo2020-05-141-1/+1
| | | | | | | * | clk: ti: omap5: Add proper parent clocks for l4-secure clocksTero Kristo2020-05-141-7/+7
| | | | | | | * | clk: ti: omap4: Add proper parent clocks for l4-secure clocksTero Kristo2020-05-141-7/+7
| | | | | | | * | clk: ti: composite: fix memory leakTero Kristo2020-05-141-0/+1
| | | | | | | |/
| | | | | | * | clk: at91: allow setting all PMC clock parents via DTMichał Mirosław2020-05-2610-10/+38
| | | | | | * | clk: at91: allow setting PCKx parent via DTMichał Mirosław2020-05-2612-13/+45
| | | | | | * | clk: at91: optimize pmc data allocationMichał Mirosław2020-05-2612-37/+20
| | | | | | * | clk: at91: pmc: decrement node's refcountClaudiu Beznea2020-05-261-0/+1
| | | | | | * | clk: at91: pmc: do not continue if compatible not locatedClaudiu Beznea2020-05-261-0/+2
| | | | | | * | clk: at91: Add peripheral clock for PTCCodrin Ciubotariu2020-05-261-0/+1
| | | | | | |/
| | | | | * | clk: socfpga: agilex: add clock driver for the Agilex platformDinh Nguyen2020-05-265-1/+528
| | | | | * | clk: socfpga: add const to _ops data structuresDinh Nguyen2020-05-263-4/+4
| | | | | * | clk: socfpga: remove clk_ops enable/disable methodsDinh Nguyen2020-05-263-6/+0
| | | | | * | clk: socfpga: stratix10: use new parent data schemeDinh Nguyen2020-05-265-41/+146
| | | | | |/