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| | | | * | clk: zynqmp: Make zynqmp_clk_get_max_divisor staticYueHaibing2020-05-261-1/+1
| | | | * | clk: zynqmp: Update fraction clock check from custom type flagsTejas Patel2020-05-261-2/+4
| | | | * | clk: zynqmp: Add support for custom type flagsRajan Vaja2020-05-262-0/+5
| | | | * | clk: zynqmp: fix memory leak in zynqmp_register_clocksQuanyang Wang2020-05-261-6/+9
| | | | * | clk: zynqmp: Fix invalid clock name queriesRajan Vaja2020-05-261-0/+5
| | | | * | clk: zynqmp: Fix divider2 calculationTejas Patel2020-05-261-5/+12
| | | | * | clk: zynqmp: Limit bestdiv with maxdivRajan Vaja2020-05-261-0/+2
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| | | * | clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slicePeng Fan2020-05-214-39/+39
| | | * | clk: imx: add imx8m_clk_hw_composite_busPeng Fan2020-05-212-0/+12
| | | * | clk: imx: add mux ops for i.MX8M composite clkPeng Fan2020-05-211-1/+50
| | | * | clk: imx8m: migrate A53 clk root to use composite corePeng Fan2020-05-203-9/+9
| | | * | clk: imx8mp: use imx8m_clk_hw_composite_core to simplify codePeng Fan2020-05-201-31/+16
| | | * | clk: imx8mp: Define gates for pll1/2 fixed dividersPeng Fan2020-05-201-18/+36
| | | * | clk: imx: imx8mp: fix pll mux bitPeng Fan2020-05-201-10/+10
| | | * | clk: imx8m: drop clk_hw_set_parent for A53Peng Fan2020-05-204-12/+0
| | | * | clk: imx: Add helpers for passing the device as argumentAbel Vesa2020-04-291-0/+29
| | | * | clk: imx: pll14xx: Add the device as argument when registeringAbel Vesa2020-04-292-7/+14
| | | * | clk: imx: gate2: Allow single bit gating clockAbel Vesa2020-04-292-8/+36
| | | * | clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock waitAnson Huang2020-04-201-11/+5
| | | * | clk: imx: clk-sscg-pll: Remove unnecessary blank linesAnson Huang2020-04-201-10/+0
| | | * | clk: imx: drop the dependency on ARM64 for i.MX8MPeng Fan2020-04-141-4/+4
| | | * | clk: imx7ulp: make it easy to change ARM core clkPeng Fan2020-04-141-2/+4
| | | * | clk: imx: imx6ul: change flexcan clock to support CiA bitratesWaibel Georg2020-04-131-1/+1
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| | * | clk: tegra: Add Tegra210 CSI TPG clock gateSowjanya Komatineni2020-05-121-0/+7
| | * | clk: tegra30: Use custom CCLK implementationDmitry Osipenko2020-05-121-2/+4
| | * | clk: tegra20: Use custom CCLK implementationDmitry Osipenko2020-05-121-2/+5
| | * | clk: tegra: cclk: Add helpers for handling PLLX rate changesDmitry Osipenko2020-05-122-0/+36
| | * | clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko2020-05-122-1/+17
| | * | clk: tegra: Add custom CCLK implementationDmitry Osipenko2020-05-123-2/+188
| | * | clk: tegra: Remove the old emc_mux clock for Tegra210Joseph Lo2020-05-121-19/+31
| | * | clk: tegra: Implement Tegra210 EMC clockJoseph Lo2020-05-123-0/+373
| | * | clk: tegra: Export functions for EMC clock scalingJoseph Lo2020-05-121-0/+26
| | * | clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo2020-05-121-0/+11
| | * | clk: tegra: Rename Tegra124 EMC clock source fileThierry Reding2020-05-124-6/+2
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| *-----. \ Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung' ...Stephen Boyd2020-06-0114-82/+443
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| | | | | * | clk: sunxi: Fix incorrect usage of round_down()Rikard Falkeborn2020-04-141-1/+1
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| | | | * | clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1Marek Szyprowski2020-05-191-1/+2
| | | | * | ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;Joe Perches2020-05-191-1/+1
| | | | * | clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542xMarek Szyprowski2020-05-131-1/+1
| | | | * | clk: samsung: Mark top ISP and CAM clocks on Exynos542x as criticalMarek Szyprowski2020-05-131-7/+9
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| | | * | clk: renesas: cpg-mssr: Fix STBCR suspend/resume handlingGeert Uytterhoeven2020-05-181-3/+5
| | | * | clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selectsGeert Uytterhoeven2020-04-301-3/+0
| | | * | clk: renesas: cpg-mssr: Add R8A7742 supportLad Prabhakar2020-04-305-0/+288
| | | * | clk: renesas: r9a06g032: Fix some typo in commentsChristophe JAILLET2020-04-141-3/+3
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| | * | clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl2020-05-022-0/+13
| | * | clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl2020-04-291-3/+11
| | * | clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl2020-04-291-5/+5
| | * | clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl2020-04-291-23/+56
| | * | clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl2020-04-291-1/+1
| | * | clk: meson: g12a: Prepare the GPU clock tree to change at runtimeMartin Blumenstingl2020-04-161-8/+22
generated by cgit v1.2.3-71-gd317 (git 2.46.0) at 2026-01-19 09:50:23 +0000