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| | | * | clk: si5341: Add silabs,xaxb-ext-clk propertyRobert Hancock2021-06-271-2/+7
| | | * | clk: si5341: Allow different output VDD_SEL valuesRobert Hancock2021-06-271-26/+110
| | | * | clk: si5341: Update initialization magicRobert Hancock2021-06-271-1/+3
| | | * | clk: si5341: Check for input clock presence and PLL lock on startupRobert Hancock2021-06-271-0/+26
| | | * | clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock2021-06-271-2/+13
| | | * | clk: si5341: Wait for DEVICE_READY on startupRobert Hancock2021-06-271-0/+32
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| | * | clk: st: clkgen-fsyn: embed soc clock outputs within compatible dataAlain Volmat2021-06-271-12/+101
| | * | clk: st: clkgen-pll: embed soc clock outputs within compatible dataAlain Volmat2021-06-271-14/+106
| | * | clk: st: flexgen: embed soc clock outputs within compatible dataAlain Volmat2021-06-271-14/+353
| | * | clk: st: clkgen-pll: remove unused variable of struct clkgen_pllAlain Volmat2021-06-271-1/+0
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| *-------. \ Merge branches 'clk-lmk04832', 'clk-stm', 'clk-rohm', 'clk-actions' and 'clk-...Stephen Boyd2021-06-2915-186/+2625
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| | | | | | * | clk: ingenic: Add support for the JZ4760Paul Cercueil2021-06-274-0/+441
| | | | | | * | clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil2021-06-272-13/+30
| | | | | | * | clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil2021-06-273-8/+6
| | | | | | * | clk: ingenic: Read bypass register only when there is onePaul Cercueil2021-06-271-8/+11
| | | | | | * | clk: Support bypassing dividersPaul Cercueil2021-06-275-29/+42
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| | | | | * | clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoCCristian Ciocaltea2021-06-271-1/+16
| | | | | * | clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea2021-06-271-8/+11
| | | | | * | clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea2021-06-271-15/+29
| | | | | * | clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea2021-06-271-4/+2
| | | | | * | clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea2021-06-271-6/+6
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| | | | * / clk: bd718xx: Drop BD70528 supportMatti Vaittinen2021-06-272-12/+5
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| | | * | clk: stm32mp1: new compatible for secure RCC supportGabriel Fernandez2021-06-282-1/+110
| | | * | clk: stm32mp1: move RCC reset controller into RCC clock driverGabriel Fernandez2021-06-271-13/+144
| | | * | clk: stm32mp1: convert to module driverGabriel Fernandez2021-06-271-43/+78
| | | * | clk: stm32mp1: remove intermediate pll clocksGabriel Fernandez2021-06-271-23/+42
| | | * | clk: stm32mp1: merge 'ck_hse_rtc' and 'ck_rtc' into one clockGabriel Fernandez2021-06-271-6/+48
| | | * | clk: stm32mp1: merge 'clk-hsi-div' and 'ck_hsi' into one clockGabriel Fernandez2021-06-271-5/+5
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| | * | clk: lmk04832: Use of match tableStephen Boyd2021-06-281-2/+4
| | * | clk: lmk04832: Depend on SPIStephen Boyd2021-06-281-0/+1
| | * | clk: lmk04832: add support for digital delayLiam Beguin2021-06-271-6/+315
| | * | clk: add support for the lmk04832Liam Beguin2021-06-273-0/+1296
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| *-------. \ Merge branches 'clk-rockchip', 'clk-amlogic', 'clk-yaml', 'clk-zynq' and 'clk...Stephen Boyd2021-06-2918-113/+449
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| | | | | | * clk: socfpga: clk-pll: Remove unused variable 'rc'Jian Xin2021-06-271-2/+1
| | | | | | * clk: agilex/stratix10/n5x: fix how the bypass_reg is handledDinh Nguyen2021-06-271-3/+8
| | | | | | * clk: agilex/stratix10: add support for the 2nd bypassDinh Nguyen2021-06-273-2/+123
| | | | | | * clk: agilex/stratix10: fix bypass representationDinh Nguyen2021-06-272-21/+91
| | | | | | * clk: agilex/stratix10: remove noc_clkDinh Nguyen2021-06-272-34/+30
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| | | | | * clk: zynqmp: Handle divider specific read only flagRajan Vaja2021-06-281-1/+9
| | | | | * clk: zynqmp: Use firmware specific mux clock flagsRajan Vaja2021-06-282-1/+30
| | | | | * clk: zynqmp: Use firmware specific divider clock flagsRajan Vaja2021-06-282-1/+33
| | | | | * clk: zynqmp: Use firmware specific common clock flagsRajan Vaja2021-06-286-6/+52
| | | | | * clk: zynqmp: pll: Remove some dead codeChristophe JAILLET2021-06-251-2/+0
| | | | | * clk: zynqmp: fix compile testing without ZYNQMP_FIRMWAREMichal Simek2021-06-252-8/+24
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| | | * | clk: meson: g12a: Add missing NNA source clocks for g12bNick Xie2021-06-091-0/+6
| | | * | clk: meson: axg-audio: improve deferral handlingJerome Brunet2021-05-241-3/+2
| | | * | clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet2021-05-201-1/+1
| | | * | clk: meson: pll: switch to determine_rate for the PLL opsMartin Blumenstingl2021-05-191-11/+15
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| | * | clk: rockchip: export ACLK_VCODEC for RK3036Alex Bee2021-05-281-1/+1
| | * | clk: rockchip: fix rk3568 cpll clk gate bitsPeter Geis2021-05-241-5/+5
generated by cgit v1.2.3-71-gd317 (git 2.46.0) at 2026-01-15 02:43:19 +0000