summaryrefslogtreecommitdiffstats
path: root/drivers/clk
Commit message (Expand)AuthorAgeFilesLines
...
| | * | clk: rockchip: Optimize PLL table memory usageElaine Zhang2021-05-111-11/+18
| | |/
| | |
| | \
| | \
| | \
| | \
| | \
| | \
| | \
| *-------. \ Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and 'cl...Stephen Boyd2021-06-2923-296/+931
| |\ \ \ \ \ \
| | | | | | * | clk: imx8mq: remove SYS PLL 1/2 clock gatesLucas Stach2021-06-141-38/+18
| | | | | | * | clk: imx: scu: Do not enable runtime PM for CPU clksNitin Garg2021-06-141-12/+18
| | | | | | * | clk: imx: scu: add parent save and restoreDong Aisheng2021-06-141-1/+28
| | | | | | * | clk: imx: scu: Only save DC SS clock using non-cached clock rateAnson Huang2021-06-141-1/+8
| | | | | | * | clk: imx: scu: Add A72 frequency scaling supportAnson Huang2021-06-141-1/+3
| | | | | | * | clk: imx: scu: Add A53 frequency scaling supportAnson Huang2021-06-141-2/+2
| | | | | | * | clk: imx: scu: bypass pi_pll enable status restoreDong Aisheng2021-06-141-1/+1
| | | | | | * | clk: imx: scu: detach pd if can't power upDong Aisheng2021-06-141-0/+1
| | | | | | * | clk: imx: scu: bypass cpu clock save and restoreDong Aisheng2021-06-141-0/+10
| | | | | | * | clk: imx: scu: add parallel port clock opsGuoniu.zhou2021-06-141-0/+8
| | | | | | * | clk: imx: scu: add more scu clocksDong Aisheng2021-06-141-2/+150
| | | | | | * | clk: imx: scu: add enet rgmii gpr clocksDong Aisheng2021-06-141-4/+18
| | | | | | * | clk: imx8qm: add clock valid resource checkingDong Aisheng2021-06-144-1/+119
| | | | | | * | clk: imx8qxp: add clock valid checking mechnismDong Aisheng2021-06-145-8/+137
| | | | | | * | clk: imx: scu: add gpr clocks supportDong Aisheng2021-06-142-0/+215
| | | | | | * | clk: imx: scu: remove legacy scu clock binding supportDong Aisheng2021-06-142-135/+81
| | | | | | * | clk: imx: Remove the audio ipg clock from imx8mpJacky Bai2021-06-141-1/+0
| | | | | | |/
| | | | | * | clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulatorAlexandru Ardelean2021-06-251-2/+2
| | | | | * | clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()Yang Yingliang2021-06-021-1/+3
| | | | | * | clk: tegra: Don't deassert reset on enabling clocksDmitry Osipenko2021-05-313-13/+1
| | | | | * | clk: tegra: Mark external clocks as not having reset controlDmitry Osipenko2021-05-311-3/+3
| | | | | * | clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttlingDmitry Osipenko2021-05-312-3/+15
| | | | | * | clk: tegra: Don't allow zero clock rate for PLLsDmitry Osipenko2021-05-311-0/+3
| | | | | * | clk: tegra: Halve SCLK rate on Tegra20Dmitry Osipenko2021-05-311-3/+3
| | | | | * | clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko2021-05-311-5/+4
| | | | | * | clk: tegra: Fix refcounting of gate clocksDmitry Osipenko2021-05-312-25/+58
| | | | | * | clk: tegra30: Use 300MHz for video decoder by defaultDmitry Osipenko2021-05-311-1/+1
| | | | | |/
| | | | * / clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audioTobias Schramm2021-05-241-2/+2
| | | | |/
| | | * / clk: vc5: fix output disabling when enabling a FODLuca Ceresoli2021-06-081-3/+24
| | | |/
| | * | clkdev: remove unused clkdev_alloc() interfacesArnd Bergmann2021-06-081-28/+0
| | * | clkdev: remove CONFIG_CLKDEV_LOOKUPArnd Bergmann2021-06-082-7/+2
| | |/
| | |
| | \
| | \
| | \
| | \
| | \
| *-----. \ Merge branches 'clk-qcom', 'clk-versatile', 'clk-renesas', 'clk-sifive' and '...Stephen Boyd2021-06-2919-92/+1414
| |\ \ \ \ \
| | | | | * | drivers: ti: remove redundant error message in adpll.cYu Jiahua2021-06-271-4/+1
| | | | | * | clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclkLokesh Vutla2021-06-221-0/+17
| | | | | * | clk: ti: add am33xx/am43xx spread spectrum clock supportDario Binacchi2021-06-082-0/+124
| | | | | * | clk: ti: fix typo in routine descriptionDario Binacchi2021-06-081-1/+1
| | | | | |/
| | | | * | clk: analogbits: fix doc warning in wrpll-cln28hpc.cYang Yingliang2021-06-011-1/+1
| | | | * | clk: sifive: Fix kernel-docYang Li2021-06-011-1/+1
| | | | |/
| | | * | clk: renesas: Add support for R9A07G044 SoCLad Prabhakar2021-06-105-0/+141
| | | * | clk: renesas: Add CPG core wrapper for RZ/G2L SoCLad Prabhakar2021-06-104-0/+883
| | | * | clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto2021-05-271-0/+1
| | | * | clk: renesas: cpg-mssr: Make srstclr[] comment block consistentGeert Uytterhoeven2021-05-271-1/+3
| | | * | clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitionsGeert Uytterhoeven2021-05-271-6/+0
| | | * | clk: renesas: r9a06g032: Switch to .determine_rate()Geert Uytterhoeven2021-05-111-12/+13
| | | * | clk: renesas: div6: Implement range checkingGeert Uytterhoeven2021-05-111-1/+7
| | | * | clk: renesas: div6: Consider all parents for requested rateGeert Uytterhoeven2021-05-111-3/+32
| | | * | clk: renesas: div6: Switch to .determine_rate()Geert Uytterhoeven2021-05-111-5/+7
| | | * | clk: renesas: div6: Simplify src mask handlingGeert Uytterhoeven2021-05-111-20/+11
generated by cgit v1.2.3-71-gd317 (git 2.46.0) at 2026-01-15 04:09:08 +0000