cachepc-qemu

commit ffa95097ee9937a799c965201381a28e0860339c
parent 6079922050b5c5db19c7e19fae7a398ff3502523
Author: Michael Roth <michael.roth@amd.com>
Date:   Wed,  9 Feb 2022 13:26:36 -0600

i386/sev: fill XCR0_IN/XSS_IN according to initial/base XSAVE state

Previously these fields were ignored in WIP SEV-SNP support for linux
guests, but the latest versions search for explicitly for
XCR0_IN=1/XSS_IN=0 when search the CPUID table for CPUID leaves 0xD/0x0
and 0xD/0x1, so set them accordingly in QEMU.

Signed-off-by: Michael Roth <michael.roth@amd.com>

Diffstat:
M
target/i386/sev.c
 | 
5
++++-

1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/i386/sev.c b/target/i386/sev.c
@@ -1244,11 +1244,14 @@ sev_snp_cpuid_info_fill(SnpCpuidInfo *snp_cpuid_info,
         /*
          * Guest kernels will calculate EBX themselves using the 0xD
          * subfunctions corresponding to the individual XSAVE areas, so only
-         * encode the base XSAVE size in the initial leaves.
+         * encode the base XSAVE size in the initial leaves, corresponding
+         * to the initial XCR0=1 state.
          */
         if (snp_cpuid_entry->eax_in == 0xD &&
             (snp_cpuid_entry->ecx_in == 0x0 || snp_cpuid_entry->ecx_in == 0x1)) {
             snp_cpuid_entry->ebx = 0x240;
+            snp_cpuid_entry->xcr0_in = 1;
+            snp_cpuid_entry->xss_in = 0;
         }
     }