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path: root/target/arm/translate.c
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* target/arm: Add TB flag for "MVE insns not predicated"Peter Maydell2021-09-211-0/+8
* target/arm: Avoid goto_tb if we're trying to exit to the main loopPeter Maydell2021-09-211-1/+33
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-4/+5
* target/arm: Take an exception if PSTATE.IL is setPeter Maydell2021-09-131-0/+21
* target/arm: Implement HSTR.TJDBXPeter Maydell2021-08-261-0/+12
* target/arm: Implement M-profile trapping on division by zeroPeter Maydell2021-08-251-2/+2
* target/arm: Implement MVE VCTPPeter Maydell2021-08-251-0/+33
* target/arm: Enforce that M-profile SP low 2 bits are always zeroPeter Maydell2021-07-271-0/+3
* accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson2021-07-211-29/+0
* target/arm: Use translator_use_goto_tb for aarch32Richard Henderson2021-07-091-11/+1
* target/arm: Use DISAS_TOO_MANY for ISB and SBRichard Henderson2021-07-091-2/+2
* tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé2021-07-091-1/+0
* target/arm: Implement MVE shifts by registerPeter Maydell2021-07-021-0/+30
* target/arm: Implement MVE shifts by immediatePeter Maydell2021-07-021-2/+66
* target/arm: Implement MVE long shifts by registerPeter Maydell2021-07-021-0/+69
* target/arm: Implement MVE long shifts by immediatePeter Maydell2021-07-021-0/+90
* target/arm: Use asimd_imm_const for A64 decodePeter Maydell2021-07-021-2/+15
* target/arm: Make asimd_imm_const() publicPeter Maydell2021-07-021-0/+57
* target/arm: Improve REVSHRichard Henderson2021-06-291-3/+1
* tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64Richard Henderson2021-06-291-1/+1
* target/arm: Add framework for MVE decodePeter Maydell2021-06-161-0/+1
* target/arm: Implement MVE LETP insnPeter Maydell2021-06-161-8/+96
* target/arm: Implement MVE DLSTPPeter Maydell2021-06-161-2/+21
* target/arm: Implement MVE WLSTP insnPeter Maydell2021-06-161-1/+36
* target/arm: Implement MVE LCTPPeter Maydell2021-06-161-0/+24
* target/arm: Add handling for PSR.ECI/ICIPeter Maydell2021-06-161-5/+106
* target/arm: Make sure that commpage's tb->size != 0Ilya Leoshkevich2021-05-201-0/+2
* target/arm: Make translate-neon.c.inc its own compilation unitPeter Maydell2021-05-101-3/+0
* target/arm: Make functions used by translate-neon globalPeter Maydell2021-05-101-8/+2
* target/arm: Move NeonGenThreeOpEnvFn typedef to translate.hPeter Maydell2021-05-101-3/+0
* target/arm: Delete unused typedefPeter Maydell2021-05-101-2/+0
* target/arm: Move vfp_reg_ptr() to translate-neon.c.incPeter Maydell2021-05-101-7/+0
* target/arm: Make translate-vfp.c.inc its own compilation unitPeter Maydell2021-05-101-2/+1
* target/arm: Make functions used by translate-vfp globalPeter Maydell2021-05-101-17/+8
* target/arm: Move vfp_{load, store}_reg{32, 64} to translate-vfp.c.incPeter Maydell2021-05-101-20/+0
* target/arm: Move gen_aa32 functions to translate-a32.hPeter Maydell2021-05-101-35/+16
* target/arm: Split m-nocp trans functions into their own filePeter Maydell2021-05-101-1/+0
* target/arm: Make functions used by m-nocp globalPeter Maydell2021-05-101-32/+7
* target/arm: Share unallocated_encoding() and gen_exception_insn()Peter Maydell2021-05-101-5/+9
* target/arm: Move constant expanders to translate.hPeter Maydell2021-05-101-24/+0
* target/arm: Enforce alignment for VLDn (all lanes)Richard Henderson2021-04-301-0/+15
* target/arm: Enforce alignment for SRSRichard Henderson2021-04-301-2/+2
* target/arm: Enforce alignment for RFERichard Henderson2021-04-301-2/+2
* target/arm: Enforce alignment for LDM/STMRichard Henderson2021-04-301-2/+2
* target/arm: Enforce alignment for LDA/LDAH/STL/STLHRichard Henderson2021-04-301-2/+2
* target/arm: Enforce word alignment for LDRD/STRDRichard Henderson2021-04-301-8/+8
* target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endiannessRichard Henderson2021-04-301-33/+45
* target/arm: Fix SCTLR_B test for TCGv_i64 load/storeRichard Henderson2021-04-301-2/+2
* target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64Richard Henderson2021-04-301-20/+15
* target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endiannessRichard Henderson2021-04-301-46/+50
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