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* target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()Frank Chang2021-10-072-13/+21
* target/riscv: Remove RVB (replaced by Zb[abcs])Philipp Tomsich2021-10-073-33/+0
* target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packhPhilipp Tomsich2021-10-072-77/+21
* target/riscv: Add rev8 instruction, removing grev/greviPhilipp Tomsich2021-10-074-79/+15
* target/riscv: Add a REQUIRE_32BIT macroPhilipp Tomsich2021-10-071-0/+6
* target/riscv: Add orc.b instruction for Zbb, removing gorc/gorciPhilipp Tomsich2021-10-074-55/+18
* target/riscv: Reassign instructions to the Zbb-extensionPhilipp Tomsich2021-10-072-41/+50
* target/riscv: Add instructions of the Zbc-extensionPhilipp Tomsich2021-10-074-1/+65
* target/riscv: Reassign instructions to the Zbs-extensionPhilipp Tomsich2021-10-072-18/+24
* target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B)Philipp Tomsich2021-10-072-78/+0
* target/riscv: Remove the W-form instructions from ZbsPhilipp Tomsich2021-10-072-63/+0
* target/riscv: Reassign instructions to the Zba-extensionPhilipp Tomsich2021-10-072-13/+23
* target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs propertiesPhilipp Tomsich2021-10-072-0/+8
* target/riscv: clwz must ignore high bits (use shift-left & changed logic)Philipp Tomsich2021-10-071-3/+5
* target/riscv: fix clzw implementation to operate on arg1Philipp Tomsich2021-10-071-1/+1
* target/riscv: Introduce temporary in gen_add_uw()Philipp Tomsich2021-10-071-2/+4
* hw/core: Make do_unaligned_access noreturnRichard Henderson2021-09-211-1/+1
* include/exec: Move cpu_signal_handler declarationRichard Henderson2021-09-211-2/+0
* target/riscv: csr: Rename HCOUNTEREN_CY and friendsBin Meng2021-09-212-16/+16
* target/riscv: Backup/restore mstatus.SD bit when virtual register swappedFrank Chang2021-09-211-1/+2
* target/riscv: Expose interrupt pending bits as GPIO linesAlistair Francis2021-09-211-0/+30
* target/riscv: Fix satp writeLIU Zhiwei2021-09-211-1/+1
* target/riscv: Update the ePMP CSR addressAlistair Francis2021-09-212-2/+3
* target/riscv: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé2021-09-143-7/+2
* accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich2021-09-141-2/+3
* target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2021-09-012-61/+26
* target/riscv: Tidy trans_rvh.c.incRichard Henderson2021-09-012-210/+57
* target/riscv: Use {get,dest}_gpr for RVDRichard Henderson2021-09-011-65/+60
* target/riscv: Use {get,dest}_gpr for RVFRichard Henderson2021-09-011-76/+70
* target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson2021-09-011-13/+6
* target/riscv: Use {get,dest}_gpr for RVARichard Henderson2021-09-011-28/+19
* target/riscv: Reorg csr instructionsRichard Henderson2021-09-013-66/+132
* target/riscv: Fix hgeie, hgeipRichard Henderson2021-09-011-18/+8
* target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson2021-09-011-8/+15
* target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson2021-09-011-18/+20
* target/riscv: Use get_gpr in branchesRichard Henderson2021-09-011-15/+10
* target/riscv: Use extracts for sraiw and srliwRichard Henderson2021-09-011-2/+12
* target/riscv: Use DisasExtend in shift operationsRichard Henderson2021-09-013-202/+125
* target/riscv: Add DisasExtend to gen_unaryRichard Henderson2021-09-012-23/+15
* target/riscv: Move gen_* helpers for RVBRichard Henderson2021-09-012-233/+234
* target/riscv: Move gen_* helpers for RVMRichard Henderson2021-09-012-127/+127
* target/riscv: Use gen_arith for mulh and mulhuRichard Henderson2021-09-011-22/+18
* target/riscv: Remove gen_arith_div*Richard Henderson2021-09-012-50/+8
* target/riscv: Add DisasExtend to gen_arith*Richard Henderson2021-09-014-90/+64
* target/riscv: Introduce DisasExtend and new helpersRichard Henderson2021-09-011-16/+81
* target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson2021-09-019-144/+144
* target/riscv: Clean up division helpersRichard Henderson2021-09-011-83/+91
* target/riscv: Use tcg_constant_*Richard Henderson2021-09-013-70/+34
* target/riscv: Add User CSRs read-only checkLIU Zhiwei2021-09-011-3/+5
* target/riscv: Don't wrongly override isa versionLIU Zhiwei2021-09-011-6/+8
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