cachepc-qemu

Fork of AMDESE/qemu with changes for cachepc side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-qemu
Log | Files | Refs | Submodules | LICENSE | sfeed.txt
commit c00640be9fc867c4668c5809c7a6a55c420acce7
parent 83363c6078aefeaa71ceb8cfe953d9c0d69f0e89
Author: Michael Roth <michael.roth@amd.com>
Date:   Thu, 26 Aug 2021 14:59:44 -0500

target/i386: set SEV-SNP CPUID bit when SNP enabled

SNP guests will rely on this bit to determine certain feature support.

Signed-off-by: Michael Roth <michael.roth@amd.com>

Diffstat:

Mtarget/i386/cpu.c | 1+


1 file changed, 1 insertion(+), 0 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
@@ -5765,6 +5765,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
     case 0x8000001F:
         *eax = sev_enabled() ? 0x2 : 0;
         *eax |= sev_es_enabled() ? 0x8 : 0;
+        *eax |= sev_snp_enabled() ? 0x10 : 0;
         *ebx = sev_get_cbit_position();
         *ebx |= sev_get_reduced_phys_bits() << 6;
         *ecx = 0;